In the fabrication of modern semiconductor devices, the technology used for packaging a ULSI chip after the completion of the fabrication processes has become more important. The packaging of a ULSI chip is important because the package must provide electrical connection to the chip, expand the chip electrode pitch for the next level of packaging, protect the chip from mechanical and environmental stress, and provide a proper heat sink to dissipate heat generated by the chip. The more advanced and more densely-packed ULSI devices require superior package performance due to their reduced package size and the resulting increased density. In some of the logic and microprocessor devices, the higher input/output terminal numbers, the higher speed and the higher power dissipation further create additional requirements for the packaging technology. An ideal packaging technology must be able to accomplish, simultaneously, larger input/output pin counts, improved heat conductance and superior electrical performance in a smaller package than was ever achieved before.
Prior to the packaging of a semiconductor device, the device is processed through back-end processing steps such as the deposition and patterning of a metal conductive layer and the coating of a silicon nitride protective layer for moisture barrier before the device can be encapsulated in one of two popular packaging techniques, i.e., a hermetic-ceramic package or a plastic package. In a hermetic-ceramic package, the chip is sealed in an environment such that it is decoupled from the external environment by a vacuum-tight enclosure. The package is usually ceramic-based and designed for high performance applications at a high cost basis. On the other hand, a chip is not perfectly decoupled from the external environment in a plastic package since it is encapsulated with a plastic material, i.e., typically an epoxy-based resin or a polyvinyl chloride. The plastic packaging technique has become more prevalent in recent years due to their easy processing and low cost. The packaging process by plastic can be automated and therefore can be carried out at a low cost.
In a typical plastic package, a chip is attached to a paddle formed in a lead frame that is made of an etched or stamped thin sheet of metal. The lead frame serves as a support around which the package is molded, and furthermore, it provides external leads in the completed package. Interconnections to the chip can be made by fine metal wire such as gold. The packaging process of encapsulation can be carried out by a transfer molding technique utilizing an epoxy resin or a PVC. The plastic resin covers the chip and forms the outer profile of the package at the same time. The external leads are then formed into their final shape after the molding process.
In the plastic molding process, a thermoset molding material such as epoxy or a thermoplastic molding material such as PVC is normally molded in large multi-cavity molds. After a molding compound enters a tool, usually pre-heated, it melts under pressure and heat, and then flows to fill the mold cavities which contain lead frame strips with their attached chips. The lead frame is normally equipped with long, fragile fingers and the chip is interconnected to these thin leads with thin gold wires of 25 .mu.m diameter. In order to avoid damaging to the fragile structure, the viscosity and the velocity of the molding compound must be precisely controlled within a desirable range. Commercially available molding compounds are designed to meet the processing requirements and can be processed at a temperature of about 175.degree. C. and at a pressure of about 6 MPa.
After a semiconductor device having a silicon nitride protective layer deposited on top is encapsulated by a plastic material, a molding stress exists between the silicon nitride layer and the encapsulating plastic layer. The stress is normally caused by the large difference in their coefficients of thermal expansion. After the semiconductor device is cooled to room temperature, the high molding stress existed in the plastic package may then cause the silicon nitride layer to crack and thus produce quality problems. To prevent this from happening, a new technique that involves the placement of a buffer coating layer on top of the silicon nitride layer prior to the plastic encapsulation process has been proposed. The buffer coating layer applied on top of the silicon nitride layer is normally of a polymeric base and acts as a lubricating layer to relieve the molding stress between the nitride and the molding compound. One of such suitable buffer coating layer is formed of a polyimide material.
Polyimides are normally derived from imidization reactions between amines and organic acids which occur in a temperature range between 130.degree. C. and 200.degree. C. Polyimides can be applied by a technique similar to that used for applying spin-on-glass materials, i.e., by spinning and curing on a wafer surface such that a planar surface is obtained for use as multi-level metalization and as a buffer layer. Polyimide is widely used in semiconductor processing due to its desirable properties such as ease of deposition, flexibility in composition, planarity as a spun film, good temperature tolerance, excellent weathering and mechanical wear properties, low pinhole density, and low dielectric constant. Most frequent uses for polyimide films in semiconductor processing are interlevel dielectrics and protective buffer coats. Similar to a photoresist material, polyimide can be made photo-sensitive by the addition of a photo-active compound. A photo-sensitive polyimide can therefore be used as a mask for opening bond pads and fuse windows on the surface of a semiconductor device by an etch-back process. When polyimide is used as a protective buffer coat, in a thickness range between about 5 .mu.m and about 80 .mu.m, the polyimide film reduces molding stress and furthermore, serves to block ionizing radiation such as alpha particles from reaching silicon.
A typical polyimide coating process is shown in FIG. 1. The polyimide coating process 10 can be started by a wafer loading step 12 during which a semiconductor wafer is first positioned in a backing chamber. The wafer is then processed in a pre-baked step 14 during which a series of pre-baking steps are carried out at a temperature of approximately 250.degree. C. The purpose of the pre-baking step 14 is to dry the wafer and reduce its moisture content on the wafer surface. After the wafer is cooled to approximately room temperature, a polyimide coating is applied to the wafer surface in step 16 while the wafer is being spun at a suitable rotational speed. The polyimide coated wafer is then post-baked in a series of oven exposures wherein the baking temperature is raised from 80.degree. C. to 95.degree. C. The total post-baking time required is approximately 5 minutes. This is shown as step 18 in FIG. 1. After the execution of the post-baking step 18, the wafer is again cooled to room temperature and then exposed in an imaging step 20 to produce a pattern on a semiconductor device for producing the necessary features such as bond pads and fuse windows. The polyimide film patterned on the wafer surface is then sent through a developing step 22 for developing the exposed features. After a developing and rinsing process is carried out, the wafer is unloaded at the last step 24.
During a conventional polyimide coating process 10 as that shown in FIG. 1, a silicon coupling agent is frequently used as an adhesion promoting layer on top of the semiconductor wafer prior to the coating of the polyimide layer. A typical silicon coupling agent has a formula of: ##STR1##
The silicon coupling agent is highly reactive with water and water is normally contained in the NMP (N-methyl-pyrrolidone) solvent. It has been found that 1% of water is normally contained in NMP. A dispersive intermediate compound which is formed between the coupling agent and water can further react with a silicon substrate to provide a desirable ionic-bonded structure to assist the adhesion. This is shown by the following equation: ##STR2##
However, when a coated polyimide precursor is exposed to ambient moisture for more than 15 minutes, the dispersed intermediate compound polymerizes itself and forms a polymer and water molecules. The water molecules are presented as water vapor at the polyimide deposition temperature and as a result, form bubbles between the polyimide film and the substrate it covers. The bubble formation presents a serious quality problem in a semiconductor device that is coated with a polyimide film.
It is therefore an object of the present invention to provide a method for depositing a polyimide film on an electronic structure that does not have the drawbacks and shortcomings of the conventional deposition method.
It is another object of the present invention to provide a method for depositing a polyimide film on an electronic structure incorporating the use of a silicon coupling agent that does not form bubble defect from water molecules generated by the silicon coupling agent.
It is a further object of the present invention to provide a method for coating a polyimide precursor containing a silicon coupling agent on a semiconductor wafer that does not produce bubble defect in the polyimide film due to a polymerization reaction of the silicon coupling agent.
It is another further object of the present invention to provide a method for coating a polyimide film on a semiconductor wafer when a silicon coupling agent is utilized by providing an improved environment of low humidity for the coating process.
It is still another object of the present invention to provide a method for coating a polyimide film on a semiconductor wafer when a silicon coupling agent is used by purging through the deposition chamber with an inert gas prior to and during the polyimide deposition process.
It is yet another object of the present invention to provide a method for depositing a polyimide film on a semiconductor wafer when a silicon coupling agent is used for adhesion promotion without bubble defect that can be carried out by purging an inert gas through the deposition chamber at a flow rate of not less than 0.5 liter/min.
It is still another further object of the present invention to provide a method for depositing a polyimide film on a semiconductor wafer by first providing a polyimide precursor containing a polyimide, a silicon coupling agent, a photo-active compound and a solvent and then depositing the precursor on the wafer surface in an environment that was purged with an inert gas.
It is yet another further object of the present invention to provide a method for depositing a polyimide film on a semiconductor wafer wherein a silicon coupling agent is used by carrying out the deposition process in a chamber that has a relative humidity of not higher than 25 %.